1. Field of the Invention
The present invention relates to method and apparatus for multiplexing an integrated circuit pin.
2. Description of the Related Art
In the field of Application Specific Integrated Circuit (ASIC), there are a number of applications, which are yet to be explored. As a result of this, manufacturers of micro processor/controller have found it necessary to design their chips in a way so as to target more than one application (or customer) with a single die and simultaneously reduce the cost of manufacturing, maximize profit and reduce time to market.
Conventional IC devices are designed with dedicated pin configuration, i.e. each pin is dedicated to a specific functionality only. This certainly imposes a problem for IC devices having a low pin count.
U.S. Pat. No. 5,686,844 discloses two embodiments of the same invention that use a memory device to store information to configure the IC device pin. Input/Output logic is also used in both the embodiments in order to transfer data to and from the IC device pin when the IC device pin is configured as a digital I/O pin.
FIG. 1 shows a system for configuring IC device pins as a block input pin or as a digital I/O pin as described in the above patent. The system 10 may be used for any type of IC device 12 that requires a clock input pin and a digital I/O pin such as a PIC16C5X type micro-controller produced by MICROCHIP TECHNOLOGY, INC.
The system 10 comprises an IC device pin 14. A memory system 16 is provided for storing a value to configure the IC device pin 14 as a clock input pin and for storing a value to configure the IC device pin 14 as a digital I/O pin. The memory system 16 is a nonvolatile memory bit. The memory system 16 may also use a volatile memory bit. However, the volatile memory bit must have a set known value upon power up of the system 10.
Input/Output (I/O) logic 18 is coupled to an output 16B of the memory system 16. The I/O logic 18 is used for writing data out of the IC device pin 14 and for reading data in from the IC device pin 14 when the IC device pin 14 is configured as a digital I/O pin, the data is transferred to and from the I/O logic 18 through a data bus 20 which is directly coupled to the I/O logic 18.
Clock logic gate circuitry 22 is coupled to the output 16B of the memory system 16 and to the IC device pin 14. The clock logic gate circuitry 22 is used for outputting a clock signal when the IC device pin 14 is configured as a clock input pin. The clock logic circuitry is comprised of an AND gate 22A having an input coupled to the output 16B of the memory system 16 and having another input coupled to the IC device pin 14, and an OR gate 22B having an input coupled to an output of the AND gate 22A and another input 23 coupled to other clock sources that may be internal or external to the IC device 12.
The memory system 16 receives program data through its input 16A. The program data will set the IC device pin 14 as a clock input pin or as a digital I/O pin. The program data will either be a high value “1” or a low value “0”. When a “1” is inputted to the memory system 16, the IC device pin 14 is configured as a clock input pin. The memory system 16 will output a “1” at its output 16B and the inverter 24 will invert the high signal “1” signal to a low signal “0”. The low signal “0” will in turn disable the I/O logic 18. With the I/O logic 18 disabled, when the IC device pin 14 goes high, the output of the AND gate 22A will go high causing the output of the OR gate 22B to go high. Thus, an external clock signal that is coupled to the IC device pin 14 will be outputted through the OR gate 22B to components in the IC device 12 that requires a clock signal to operate. Another input 23 to the OR gate 22B is coupled to other clock source signals. These other clock source signals may be internal or external to the IC device 12. When the IC device pin 14 is configured as a digital I/O pin, the clock logic gate circuitry 22 may still send out a clock signal. However, the clock signal sent from the OR gate 22B has to come from the one of the other clock source signals that may be sent through input 24 of the OR gate 22B. For most IC devices 12 and applications, only one clock source is active.
When a low value “0” is inputted to the memory system 16, the IC device pin 14 is configured as a digital I/O pin. The memory system 16 will output a low signal “0” at its output 16B and the inverter 24 will invert the low signal “0” signal to a high signal “1”. The high signal “1” will enable the I/O logic 18.
The US patent as described above explains how to reuse one pin for different functionalities such as reset, clock or general-purpose I/O functionalities. It also describes how to share a single I/O for either reset/clock functionality or general I/O functionality by using a single configuration bit to configure the device into either of the functionalities.
While this idea is very useful in the sense that same die can be marketed as two devices (with Reset/Clock and with I/O functionality), it cannot be used for a normal package where both reset/clock and general I/O are present on dedicated pins. To fulfill this requirement, a different die is required as said patent uses a single I/O pad for this multiplexing. This amounts to again a new product design & testing cycle.
Also, when used for Reset functionality, the pad behaves as an input pin only. This limits the application, as the IC device cannot reset external devices.
Therefore, a need exists to provide a method and system in which the same die can be used for different configurations.